1. The Field of the Invention
The present invention relates generally to mechanisms for synchronous data transfer between two circuits. More specifically, the present invention relates to dynamic phase alignment of a clock and data signal using an adjustable clock delay line.
2. Background and Relevant Art
Electronic circuitry has become critical to the functionality of many common devices and systems. In order to accomplish a desired function, it is often desirable for one circuit to communicate with another. The communicating circuits may be on the same chip or even on different chips. Sometimes, the data communicated between the circuits has validity implied from the timing of the data relative to another signal such as a clock. This type of data transfer is often referred to as synchronous data transfer.
In chip-to-chip source synchronous data transfer, a clock signal and a data signal are transmitted from the source circuit. The clock is used in the receiving circuit to time the sampling of the incoming data. At higher transfer rates, it is particularly important that the clock is kept in alignment with the ideal sampling point of the data eye at all times. Accordingly, in the gigabit per second data rate range, dynamic phase alignment is important to compensate the clock and data skew by adaptively keeping the clock and data signals in the desired phase relationship.
At lower data rates, a technique called static phase alignment is often used to set the desired phase relationship. Like static phase alignment, dynamic phase alignment adjusts the data and clock signal phase relationships over variations of process corners, supply voltages and temperatures. Unlike static phase alignment, however, dynamic phase alignment operates adaptively, often at the granularity of a single bit. In other words, the phase alignment is typically compared each time a bit is received, and adjusted if appropriate. The dynamic phase alignment thus allows for more layout flexibility at the package and board level than static phase alignment.
FIG. 6 illustrates a conventional PLL-based dynamic phase adjustment circuit 600. Referring to FIG. 6, the input clock signal 602 goes into a Phase Locked Loop (PLL) 611, which generates multiple phases of the clock. In the illustrated case, there are eight clock signals generated that are spaced in increments of 45 degrees. Accordingly, the clock signals include clock signals CK0, CK45, CK90, CK135, CK180, CK225, CK270 and CK315. The clock signals of the different phases then allow the registers 612 to sample the input data signal 601 at slightly different times evenly spread through a clock cycle. The outputs of the registers 612 go to the edge detect and data decision block 613. The edge detect and data decision block 613 identifies the data edge and selects a correct data sample that is within the data window defined by the data edge.
In FIG. 6, the data sample is picked from the eight register outputs driven by evenly spaced phases of the clock. More phases would provide better accuracy for the sampling to be closer to the ideal sampling point that is close to the middle of the data window. In other words, FIG. 6 describes an over-sampling approach which has better sampling resolution with more phases available. However, it is difficult to generate more than eight phases using a PLL. Consequently, the sampling resolution of the PLL-based dynamic phase adjustment circuit 600 of FIG. 6 is limited. Furthermore, a PLL is usually located at a fixed place on the chip. If the input data and the input clock do not happen to be in close vicinity, globally routed clocks from the PLL will more likely lose their evenly spaced phase relationship.
FIG. 7 illustrates another conventional dynamic phase alignment circuit 700. Referring to FIG. 7, the input data 701 goes into a multi-tap delay line 711 to generate multiple delayed replicas of the data input. The delayed data replicas are then fed to registers 712. A single clock signal 702 is used by each of the registers 712 to sample the delayed replicas of the data. The outputs of the registers 712 then go to the edge detect and data decision block 713. Once again, the edge detect and data decision block 713 identifies the data edge and selects a correct data sample that is within the data window defined by the data edge.
The multi-tap delay line dynamic phase adjustment circuit 700 of FIG. 7 may provide better sampling resolution than the PLL-based dynamic phase adjustment circuit 600 of FIG. 6. The improved sampling resolution may be achieved in FIG. 7 by using delay elements that have small propagation delay. However, since the data and clock signal phase relation is unknown, the input data is delayed for at least one clock period to exhaust all possible phase states. Furthermore, fine resolution of each delay element means large number of data replicas in one clock period. In a typical source synchronous application such as SPI-4.2 where one clock is sent along with 16 data bits, 16 delay lines are needed. As a result, the total number of delay elements and the associated flip-flops could force the dynamic phase alignment circuit to be quite large and thus impractical.
Accordingly, what would be advantageous is a dynamic phase alignment circuit that may have better sampling resolution without being inordinately large and complex.